Incomplete Testing of System-on-Chip (SoC)

System on Chip Testing

Modern electronic devices such as smartphones, tablets, and digital cameras rely heavily on System-on-Chip (SoC) technology. These chips integrate multiple processing cores and functional blocks on a single chip, allowing devices to perform many tasks efficiently. However, as the number of cores increases, the cost and time required for testing the chip also increase significantly. In some cases, the cost of testing may even exceed the manufacturing cost of the chip.

In our research, we explored a different approach called incomplete testing, which aims to reduce testing cost while maintaining acceptable system performance. Instead of testing every component of the SoC thoroughly, our method selectively skips testing certain parts of the chip whose errors have minimal impact on the final output.

This idea works particularly well for applications such as multimedia processing, image display, and video streaming, where small errors in output may not be noticeable to human perception. For example, slight variations in pixel values in a video frame may not affect the viewing experience significantly. Therefore, testing for such components can be relaxed to reduce overall testing overhead. 643182e1-60a0-4a37-b08b-13868e3…

The proposed method identifies fault-tolerant output paths in the circuit and avoids testing hardware components that only affect those outputs. By doing this, the number of test vectors and testing operations can be reduced. As a result, key testing parameters such as Test Data Volume (TDV), Test Access Time (TAT), and Test Power (TP) can be significantly lowered.

Experimental results using standard benchmark circuits show that incomplete testing can reduce testing cost and resources substantially while only slightly reducing fault coverage. In many cases, the approach achieved around 52% reduction in test data volume, about 48% reduction in test time, and nearly 50% reduction in test power, while the reduction in fault coverage remained relatively small.

In conclusion, incomplete testing provides a practical and efficient strategy for testing complex SoC devices. By accepting a small trade-off in accuracy for error-tolerant applications, manufacturers can significantly reduce testing cost and make electronic devices more affordable.